With the advent of uniprocessor personal computers, multiprocessor server systems, home networking, communications systems, routers, hubs, switch fabrics, cell phones, PDA's, and mass storage servers, technology has rapidly advanced in order to support the exchange of digital data between these and similar devices. To this end, new protocols have been developed to adapt to the use of the digital data format, instead of the older analog data format. Standards in communications between the ever increasing number of different devices capable of digital data transmission and reception, are evolving. Communication between a telecommunications base station and a cell phone is a primary example. Another example is PC-centered home network communicating with numerous electronic appliances. The implementation of these standard protocols is a nontrivial problem which must be addressed at all levels during both software and hardware development. Moreover, mobile systems, like cell phones, require lower operating power with added features and performance.
As one example, the Integrated Services Digital Networks (ISDN) protocol is one particular format which has been adopted to support digital data telecommunications from various sources, including digital telephones and faxes, personal computers and workstations, video teleconferencing systems, and others. Extensions of the ISDN protocol include the broadband ISDN (BISDN) protocols which support the exchange of large files of data and/or data with strict time restrictions, such as full motion video. One of these broadband ISDN protocols, the Asynchronous Transfer Mode (ATM) protocol, is being broadly accepted in the telecommunications industry. Other protocols, like Internet Protocol, are also very popular, especially since voice over IP is rapidly gaining acceptance. IP, Ipv6, TCP, UDP, MPLS, UMTS, GPRS, CDMA, GSM, Ethernet, WAP, H.323, MGCP, SIP, RTP, Frame Relay, PPP, SS7, X25 are some other protocols beyond ATM.
Data formats for the data packets of the various different protocols vary greatly. Broadly, they can be described as: 1) Perfectly-sized packets and 2) imperfectly-sized packets. Perfectly-sized packets are octal multiples—namely those comprised of 16, 32, 64 or 128 bytes. These find applications in computing and communications memories, and hence, memory device data architectures—stand alone or embedded—which adhere to ×4, ×8, ×16, ×32 or ×9, ×18 data formats (with parity). Perfect-sized packets optimize bandwidth from the memory.
Imperfectly-sized packets are those which 1) utilize non-octal multiples, and, 2) utilize a data format which does not adhere to a length=2n bits, where n is an even number. For example, in some Ethernet applications, data packet size can be 20 bytes. Another example is packet-over-sonet where minimum data transfer size is 40 bytes. Hence, with traditional RAM's, one will incur a bandwidth inefficiency while reading and writing out of such memory devices.
In order to adhere to one protocol, and maximize bandwidth and latency, a memory core has to be organized architecturally, in one manner. In order to accommodate several protocols in the same memory, where bandwidth and latency are optimized, the memory core architecture has to be different.
In essence, the ATM protocol implements time-division concentration and packet switching to connect two or more end users through a public or private switched network, including the routers, switches and transmission media. Generally, streams of data are divided into time slots (cells) which are made available on demand (in contrast to the Synchronous Transfer Mode where each slot is preassigned). In ATM, a standard cell is 53 bytes long, with the first 5 bytes being the header and the following 48 bytes containing user data. The number of data bytes in nonstandard cells can be as small as few bytes, to as large as 4 Kbytes, depending on the protocol used. The header includes fields for flow control data and management, virtual path and virtual channel identifiers, and a payload identifier, and generally defines the packet switching of each cell. The user data bytes contain the user data itself, along with an adaptation layer (header and trailer) which identifies the data type, data length, data starting and ending bytes, etc.
There are several means of packet switching used in protocol-based systems. One method uses shared-memory switches. This shared memory is also called communication system memory in the wired communication industry (routers, servers, network/switch fabrics etc). Here, the user part of each cell is received through a corresponding port and stored in memory. In accordance with a corresponding timing protocol, these data are accessed through a second designated port to complete the switching of the user part of the packet.
Current shared-memory switches are constructed using static random access memory (SRAM) devices and dynamic random access devices (DRAM). In comparison with dynamic random access memories (DRAMs), SRAMs have a simpler interface, do not require periodic refresh of the data, and are typically faster. However, SRAMs are more expensive, consume much more power, and have lower cell densities. While memory speed remains important in many applications, including those involved with telecommunications, increasing attention must be made to the factors of cost, size and power consumption in order to remain competitive in the marketplace. Hence, a need has arisen for shared-memory switch which has the high performance of an SRAM and the lower cost and reduced power consumption of a DRAM. RLDRAM I/II™, FCRAM™, DDRSDRAM are some of the recent DRAM's that are trying to serve these requirements, with some, but not complete, success. Among other things, all of the above memories utilize a data format that is an even multiple of eight (or byte oriented) −8, 16 or 32 (9 or 18 with parity), which does not maximize bandwidth and utilization. In addition, the memory used in portable electronic appliances (e.g., cell phones) used for any communication, are also ‘packet data oriented’. To enhance bandwidth at minimum operating power, a need has arisen to optimize memory architecture—although, the transmitting and receiving ports are not many.